Thus, only requiring access to main memory if it’s absolutely necessary. Wrapping their processors with lots of cache.Well, to correct these issues, Sony alleviated the constant need for memory by: That is… multiple independent components trying to access main memory at the same time, causing congestion. Whether we want it or not, with the amount of traffic happening inside the Emotion Engine, this design will eventually suffer the consequences of the Unified memory architecture or ‘UMA’. Bear in mind that while slice mode reduces stalls on the main bus, it does so at the cost of slowing down the overall DMA transfer. This modus operandi is called slice mode and is one of the many modes available on this DMA unit. This leaves a small window to perform other DMA transfers in parallel (up to ten) or let the CPU use the main bus. The resulting setup provides a theoretical 3.2 GB/sec, so rest assured that memory latency is not an issue in this console!Īt one corner of the Emotion engine there is a powerful DMA Controller or ‘DMAC’ that transfers data between main memory and Scratchpad or between main memory and any component inside the EE.ĭata transfers are done in batches of 128-bits, but here is the interesting part: Every eight batches, the main bus is temporarily unlocked. However, the RAM chips are strategically placed by following the dual-channel architecture, which consists in connecting both chips using two independent 16-bit buses (one bus per chip) to improve data throughput. You can guess where the congestion will emerge.Īt first, this can be a little disappointing to hear, considering the internal bus of the Emotion engine is as wide as 128 bits. The type of memory used is RDRAM ( déjà vu!) which is accessed through a 16-bit bus. Next to the Emotion Engine are two blocks of 16 MB of RAM, giving a total of 32 MB of main memory. This is a peculiar block as it doesn’t follow the IEEE 754 standard, most evident with its absence of infinity (computed as 0 instead). The core is complemented with a dedicated floating point unit (identified as ‘COP1’) that accelerates operations with 32-bit floating-point numbers (also known as floats in C). Memory management unit: Interfaces memory access with the rest of the system.16 KB of Scratchpad RAM: Also known as ‘Fast RAM’.This is done by including extra circuitry that can identify which places in memory are more often requested. It also implements a prefetch function to cache instructions and data before they are requested.24 KB L1 cache: Divided into 16 KB for instructions and 8 KB for data.2-way superscalar: Up to two instructions are executed in parallel.These registers are accessed through a 128-bit bus, while the rest of the CPU uses an internal 64-bit bus.They are better managed using multimedia instructions and are very useful for vector processing. 32 128-bit extra registers: Another enhancement.Not quite, Sony enhanced the ISA by adding some instructions from MIPS IV (prefetch and conditional move) along with their own SIMD extension called multimedia instructions. Wait, is it me or this is the same ISA found on a competitor’s console?. MIPS III ISA: A 64-bit RISC instruction set.The processor provides the following features: This is the first chip that starts executing instructions after the console is turned on. The main core is a MIPS R5900-compatible CPU with lots of enhancements. The rest are at the CPU disposal to speed up certain tasks. This chipset contains multiple components, one of them being the main CPU. This machine is nowhere near as simple as the original PlayStation was, but we will see why it didn’t share the same fate of previous complicated consoles.Īt the heart of this console we find a powerful package called Emotion Engine or ‘EE’ designed by Sony and running at ~294.91 MHz. The PlayStation 2 was not one of the most powerful consoles of its generation, yet it managed to achieve a level of popularity unthinkable for other companies. This architecture went through many revisions, more details below The original design (Implemented on revision 'SCPH-10000').Įach data bus is labelled with its width and speed. I presume the chip at the bottom right corner is the 4 MB BIOS ROM Motherboard with important parts labelled Diagram Main architecture diagram Thanks to the donations received, I was able to purchase this model and take a proper photo to allow me identify most of the chips. Showing revision 'GH-001' from model SCPH-10000 only released in Japan. If you use accessibility tools or legacy browsers, switch to the ‘classic’ edition.
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